1. Field of the Invention
The present invention relates to a method of processing a polysilicon film and more particularly, to a method of processing a polysilicon film formed on a single-crystal silicon substrate, which is used in a fabrication process of a semiconductor device such as a bipolar transistor and an MOS transistor.
2. Description of the Related Art
Recently, a selective etching technique of a polysilicon film on a single-crystal silicon substrate has become very important in LSI fabrication. The technique is used for forming an emitter opening during the fabrication of a bipolar transistor having a polysilicon base electrode connected to a graft base. This technique will be described concretely below referring to FIG. 1.
FIG. 1 shows a step of fabrication process of a bipolar transistor in which the above-described conventional technique is used.
In FIG. 1, silicon dioxide films 2 for isolation are formed on a single-crystal silicon substrate 1 by selective oxidization. On the surfaces of the films 2 and the exposed surface of the substrate 1, a P.sup.+ -polysilicon film 3 having a thickness of 200 to 300 nm is deposited, and on the film 3 a silicon dioxide film 4 having a thickness of 200 to 300 nm is deposited.
In an active region formed by the oxide films 2 of the substrate 1, a graft base area 6 is formed near the surface of the substrate 1 and an emitter opening is formed in the oxide film 4 and the polysilicon film 3. The polysilicon film 3 is patterned to form a base electrode.
An N-emitter region 8 and a P-active base region 7 are formed in a portion of the substrate which is facing the emitter opening. In the emitter opening, a side wall 10 of a silicon dioxide film is formed on the side surfaces of the polysilicon film 3 and the silicon dioxide film 4, and an emitter electrode 9 of an N.sup.+ -polysilicon film is formed on the surfaces of the sidewall 10, the emitter region 8 and the silicon dioxide film 4.
The bottom end of the emitter opening should be positioned at a level which is almost the same as that of the substrate 1 (or the graft base region 6) so that the graft base region 6 and the active base region 7 may be connected to each other; however, in FIG. 1, the bottom end of the emitter opening is positioned near the bottom end of the graft base region 6 due to overetching. In addition, the bottom end of the spacer 10 is nearly extended to the bottom end of the graft base region 6.
In the process of forming the emitter opening, first, an unmasked portion of the silicon dioxide film 4 is selectively removed by the anisotropic etching technique such as the reactive-ion etching (RIE) technique using a fluorine gas or the like. Therefore, a portion of the polysilicon film 3 thus exposed is selectively removed by the anisotropic etching technique such as the RIE technique using a chlorine gas or the like.
In this process, it is impossible to selectively etch one of the P.sup.+ -polysilicon film 3 and the single-crystal silicon substrate 1. Besides, it is extremely difficult to etch the polysilicon film 3 without etching the substrate 1 with regard to the present etching rate stability and etching uniformity. Accordingly, the polysilicon film 3 tends to remain partially on the substrate 1 due to insufficient etching, or the substrate 1 tends to be overetched.
If the polysilicon film 3 partially remains on the substrate 1, a problem arises because the emitter region 8 and the graft base region 6 are short-circuited to each other through the remainder of the film 3.
If the substrate 1 is overetched a, sufficient interconnection between the graft base region 6 and the active base region 7 cannot be obtained, as shown in FIG. 1. As a result, a problem arises because the base resistance will increase and punch through will occur between the emitter region 8 and a collector region (not shown).
The above-described process of selective etching of the polysilicon film is also used in a process of forming a node portion of a memory cell of static random access memory (SRAM) composed of MOS transistors.
FIG. 2 shows a step in the fabrication process of an SRAM in which the above-described conventional etching technique is used.
As shown in FIG. 2, silicon dioxide films 12 for isolation are formed on a single-crystal silicon substrate 11 by selective oxidation. In an active region formed by the oxide films 12 of the substrate 1, the surface area of the substrate 11 is covered with a silicon dioxide film 15, as a gate insulator. The film 15 is selectively removed at a node portion N of an SRAM memory cell. A gate electrode 16 of a N.sup.+ -polysilicon film is formed on the film 15. A source region 13 and a drain region 14 are formed in the substrate 11 in self-alignment with respect to the gate electrode 16. The surface of the substrate 11 is partially exposed from the film 15 at the node portion N, and at the exposed area of the substrate 11, a concavity A is formed by etching.
The reason why the concavity A is formed is as follows: during the selective etching process of the polysilicon film to form the gate electrode 15, the etching action affects the exposed surface area of the substrate 11. Besides, the etching rate of the phosphorus diffusion region in the substrate 11, that is the source region 13 and the drain region 14 in FIG. 2, is larger than the etching rate of the other region. Therefore, the exposed surface area of the substrate 11 at the node portion N is easy to be etched.
Since the concavity A induces crystal defects in the substrate 11, a problem arises because a minute node leakage occurs to degrade the data storing characteristic of the SRAM.